Keynotes

Dr. Takefumi Miyoshi received his Ph.D. from the Interdisciplinary Graduate School of Science and Engineering at Tokyo Institute of Technology, in 2007. He is a Director at e-trees.Japan, Inc. and an Adjunct Professor at the Center for Quantum Information and Quantum Biology (QIQB), The University of Osaka. He is also Co-founders and CTO of QuEL, Inc. His research interests include reconfigurable system, computer architecture, compiler, and quantum computing.

The rapid advancement of AI is driving unprecedented demand for computing capability, motivating the exploration of new computing paradigms beyond conventional semiconductor scaling. Quantum computing is widely regarded as one of the most promising approaches to addressing this challenge. This talk presents the architectures, key technologies, and implementation challenges of scalable control systems for quantum computers. It discusses system architectures, microwave signal generation, synchronization, real-time signal processing, and low-latency feedback, together with our recent work on scalable control systems. Practical quantum computers require scalable real-time control systems capable of coordinating a large number of control modules with deterministic timing and reliable communication. This challenge extends beyond quantum devices and spans the entire technology stack, from integrated circuits and RF front-ends to system architecture and hardware-software co-design. Advances across this technology stack will play a key role in enabling quantum computers to support the future of AI and next-generation computing.

Maciej J. Ogorzalek is Honorary Professor and Head of the Department of Information Technologies, Jagiellonian University Krakow, Poland ‐ the oldest (1364) and most prestigious higher education institution in the country. He held many visiting positions in Denmark, Switzerland, Germany, Spain, Japan, Hong Kong. 2006‐2009 he held the Chair of Biosignals and Systems, Hong Kong Polytechnic University under the Distinguished Scholars Scheme. In 2019 visiting professor at the Integrated Systems Lab. Swiss Federal Institute of Technology Lausanne, honorary guest professor Kyoto University, in 2023 Guest professor under Top Global University Project Waseda University, Tokio Japan. His research interests include nonlinear circuits and systems, biomedical signal processing, analysis and design of next generation 3D integrated circuits, Machine learning and AI application. Author or co‐author of over 380 technical papers published in journals, book chapters and conference proceedings, author of the book Chaos and Complexity in Nonlinear Electronic Circuits (World Scientific, 1997). He served as Editor‐in‐Chief of the Circuits and Systems Magazine 2004‐2007, Associate Editor for the IEEE Transactions on Circuits and Systems Part I, 1993‐1995 and 1999‐2001, he was elected Member of the Editorial Board Proceedings of the IEEE 2004‐2009. He also served on the Editorial Boards of the Journal of the Franklin Institute, the International Journal of Circuit Theory and Applications and Editorial Board of the NOLTA Journal (Japan). Dr. Ogorzalek is an IEEE Life-Fellow. He served the IEEE Circuits and Systems Society including 2008 Society President. He was CAS Society Distinguished Lecturer (2004‐2005) and received the 2002 Guillemin‐Cauer Award and IEEE‐CAS Golden Jubilee Award. He received the IEEE CAS Distinguished Service Award and the Medal of National Education (Poland). He has been among organisers of several conferences, including ECCTD, NOLTA, ISCAS, IEEE COC, ESSCIR. He was elected IEEE Division 1 Director, Member of the IEEE Board of Directors 2016-2017. He is elected Ordinary Member of the Polish Academy of Sciences and Chair of the Engineering Section/Member of Academia Europaea.

Specialized hardware becomes the most important component of all new electronic systems. There are more and more new applications appearing in the picture with enormous memory sizes, alllowing enormous data flows and enabling Artificial Intelligence (AI) in various domains of applications. Further performance improvements are needed in terms of power consumption, speed of operation, communication and storage capabilities. Data transfer bottleneck, power consumption and scalability become major obstacles to be overcome. There are new concepts like in-memory computing being tested and new technologies apart from standard CMOS, including 3D integration, chiplets, 2D materials just to mention a few, which can bring new solutions. 3D integration and chiplet concepts offer unprecedented opportunities by allowing blocks fabricated in heterogeneous technologies to be integrated in one chip. This allows for combination and integration of microprocessors, memories, RF circuitry, sensors, batteries and hyper-capacitors, energy harvesting blocks, biological and chemical sensors and many new types of building blocks built in different technologies in one chip. However innovation is needed for new developments. AI revolution and new computing ideas require still better solutions! We will discuss a new design paradigms for next-generation heterogeneous 3D computing systems, starting from high-level information and energy-flow models. This approach departs from bottom-up approaches that evolve and combine existing fabrication technologies. This disruptive paradigm will encompass the generation of system spatial layout in free 3D (unconstrained) geometry by intelligent automated design procedures. Given a specific functionality, technological requirements and constraints, this approach will yield an application-specific geometry in 3D, with possibly unconventional features. Standard assumptions concerning the use of “planar processes” will be set aside in the overall system embodiment. Conversely, the system components will use existing IP blocks and technologies.

Takuya Yasui is the Director of TSMC’s Design and Technology Platform and leads the Japan Design Center。Since joining TSMC in 2020, he has successfully established and expanded the Japan Design Center, driving the development of advanced technology design platforms and providing crucial customer support to leverage these technologies. Mr. Yasui began his career in 1993 at Matsushita Electric Industrial Co., Ltd. (now Panasonic Corporation) after graduating with an MS in Information Technology from Hiroshima University. During his time there, he specialized in semiconductor design methodology, physical design, and digital ASIC development. In 2015, he transitioned to Socionext Inc., a joint venture between the system LSI businesses of Panasonic and Fujitsu, where he continued to lead advanced design teams.

In addition to advanced logic, advanced packaging has become essential to meet the high performance, power, and bandwidth demands of next-generation AI systems. Advanced packaging continuously increases communication bandwidth through UCIe, while silicon photonics improve energy efficiency and connectivity within AI datacenters. To solve the heating and power delivery issues of 3D-stacked chips, new thermal optimization techniques and vertical power delivery networks (PDN) are applied. Additionally, 3Dblox plays a crucial role in standardizing and simplifying the design of these complex, multi-die 3D chips