Student Paper Award
Student Paper Award Winners
Sota Nakagawa, Hosei University, Japan
“A Hardware-Efficient Ergodic Sequential Logic Central Generator for Multi-Legged Robot Control”
Hao-Yu Lu, National Cheng Kung University, Taiwan
“A Compact Digital Compute-in-Memory Macro Based on Ferroelectric 8T Non-volatile SRAM for Normally-off Edge Intelligence”
Yuki Majima, Tohoku University, Japan
“Low-Latency AER Communication Module for Scalable Analog CMOS Spiking Neural Networks”
Meysam Shayestehfar, University of Pavia, Bridgecom Semiconductors, Italy
“A Highly Linear Inductor-Less Wideband Single-to-Differential LNTA in 22-nm FDSOI”
Wei-Han Chen, National Taiwan University, Taiwan
“A 5-GHz Fractional Output Divider with a Segmented-TDC-Based DTC Background Calibration Achieving –245.5-dB Worst-Case Jitter FoM”
Runners-up
Jiajun Li, University of British Columbia, Canada
“A PWM Pixel with In-Pixel Time Domain Correlated Double Sampling”
Taegyun Kim, Inha University, Korea
“Noise-Aware Optimization for Low-Quantum-Cost and Error-Resilient Quantum Arithmetic Circuits”
Agile-X Chip Design Contest
Joint Grand Prize
Team Supernova, Hening Qin and Hitoshi Tabata, The University of Tokyo, Japan
“A RISC-V-Assisted Gate-Array Row Engine for sMTJ/FTJ-Inspired RBF Inference”
Team Toyohashi RISC-V Chips, Nuttapat Tamprasert, Yukinori Sato, and Kou Ishikura, Toyohashi University of Technology, Japan
“Int2FP: A Bidirectional 8-Bit INT/FP Converter with SoC Integration and Verification via Chisel and Chipyard”
Outstanding Design Prize
Team ByteMonks, Mohit Jagini, Nanda Pammi Mitra, and Madhav Rao,
“A 6-Bit Hyperdimensional Computing Coprocessoron Agile-1L Gate Array”
Team acsl, Mizuki Tanaka, Kenta Sasaki, and Kuta Yamamura,
“Design of a Binary Neural Network Template-Matching Classifier for Agile-Chip”
Certificate of Completion
Team Dugalba Tec., Uriel Jaramillo-Toral, Susana Ortega-Cisneros, and Iraam Antonio Lopez-Salas, Dugalba Tec / CINVESTAV / National Technological Institute of Mexico, Mexico
“Open-Source Hand-Drawn Design of a 4-Bit Ripple-Carry Adder Using AX180 Minimal Fab”
Team slab choco, Nagisa Yoshikawa and Ryuto Matsunaga, Nagasaki University, Japan
“Design of LED Display Controller with Dynamic PWM and Scroll Control for Agile-Chip”
Team slab gumi, Hiromu Matsuzaki and Haruki Funyu, Nagasaki University, Japan
“Grayscale Conversion and Binarization Conversion for Agile-X”
Team slab anko, Kento Nakai, Masahiro Kiyota and Shinka Nagahashi, Nagasaki University, Japan
“Secure Commit Firewall for Firmware Update on the Agile-X Gate Array”
Team vikings, Antoine Bretaux, Jean-Claude Angélique and Matthieu Denoual, ENSICAEN / GREYC / LPC Caen / Pantechnik, France
“An Agile-X Silicon Test Chip for Investigating Single-Event Under Ion Irradiation”